发明名称 Messaging mechanism for inter processor communication
摘要 An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.
申请公布号 US7996574(B2) 申请公布日期 2011.08.09
申请号 US20070800091 申请日期 2007.05.03
申请人 EMC CORPORATION 发明人 GUPTA REEMA;WANG YAO;TRINGALE ALESIA
分类号 G06F3/00;G06F11/00;G06F15/16 主分类号 G06F3/00
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