发明名称 Signal bus, multilevel input interface and information processor
摘要 A multilevel input interface device connected to a signal bus including one or more data lines that transmit an M-level signal and a clock line that transmits a transmission clock signal indicating the timings of reading level information for the M-level signal, includes: a threshold value generation unit that produces a plurality of voltage outputs as a plurality of variable comparison reference signals according to the level-varying supply voltage; a level detection unit that compares, in synchronization with the transmission clock signal, the M-value level signal with the variable comparison reference signals and generates a logic output corresponding to an instantaneous value of the M-level signal; and a logic circuit unit that converts the logic output to a data signal.
申请公布号 US7996705(B2) 申请公布日期 2011.08.09
申请号 US20070001911 申请日期 2007.12.13
申请人 SEIKO EPSON CORPORATION 发明人 TAKEUCHI KESATOSHI
分类号 G06F1/04;H03K3/00 主分类号 G06F1/04
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