Methods and apparatus for providing an efficient FFT memory addressing and storage scheme

摘要

FFT butterfly data sets may be stored in memory in a predetermined order. Such an order may allow a butterfly data set to be read from a single memory address location. The memory addressed may be computed by an address rotary function depending on the butterfly and stage of the FFT. Addressing the memory in such a manner may allow each butterfly data set of a subsequent FFT stage to be stored to a single memory location. Shuffle registers may delay the writing of FFT butterfly results to the memory until most of the data corresponding to a particular butterfly operation has been computed. The shuffle registers may rearrange and combine the results of one or more butterfly operations in a different manner from which they have been computed. Combining the results in this manner may allow a subsequent FFT stage to access data by addressing a single memory location.