| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a drive circuit in which both variation of a trailing timing and a rising timing of output voltage can be reduced, and a display device including the drive circuit. <P>SOLUTION: A buffer circuit 1 includes an inverter circuit 10 connected in series each other and an inverter circuit 20. The inverter circuit 20 has a transistor Tr<SB>21</SB>and a transistor Tr<SB>22</SB>being in parallel relation and a threshold correcting circuit 21 performing correction of gate voltage Vg of these transistor Tr<SB>21</SB>, Tr<SB>22</SB>. The threshold correcting circuit 21 sets voltage corresponding to threshold voltage V<SB>th1</SB>of the transistor Tr<SB>21</SB>or threshold voltage V<SB>th1</SB>of the transistor Tr<SB>21</SB>as offset for a gate of the transistor Tr<SB>21</SB>. The threshold correcting circuit 21, further, sets voltage corresponding to threshold voltage V<SB>th2</SB>of the transistor Tr<SB>22</SB>(not illustrated) or threshold voltage V<SB>th2</SB>of the transistor Tr<SB>22</SB>as offset for a gate of the transistor Tr<SB>22</SB>. <P>COPYRIGHT: (C)2011,JPO&INPIT |
