| 摘要 |
The adder (121) provided in a trigger delay control circuit (12) adds a fixed delay value (203), which is transmitted from a CPU (16) and which is in clock units, to time stamp information (202), which is obtained by a software trigger detection circuit (114) and which is in clock units, and outputs a time stamp (204) including a trigger delay of a given time length. The comparator (122) compares a cycle timer value (201) that has been output from a cycle timer operation circuit (113) with the time stamp (204) that has been output from the adder (121) and that includes the trigger delay of the given time length, and when the cycle timer value (201) exceeds the time stamp (204) including the trigger delay of the given time length, the comparator sends a trigger signal (205), which commands that exposure be started, to a sync-signal generator circuit (13). |
