发明名称 SYSTEM AND METHOD FOR PROCESSING MEMORY FAULT
摘要 PROBLEM TO BE SOLVED: To provide a memory fault processing system for efficiently linking switching to a spare memory and page blocking to prevent a system down. SOLUTION: The memory fault processing system includes: a memory device 2 having memory chips 21 and a spare memory chip 22; a sum-total-number-of-occurrences counting part 31 for counting a sum total number of occurrences of faults of the memory chips 21; a switching-to-spare-memory-chip part 32 for switching the memory chip 21 that is faulty if the sum total number of occurrences exceeds a sum total threshold to the spare memory chip 22; a counting-in-units-of-cache-lines part 33 for counting the number of occurrences of faults after switching in units of cache lines; and a page blocking part 34 for blocking a memory page if the number of occurrences in units of cache lines exceeds a threshold in units of cache lines before the sum total number of occurrences after switching exceeds the total sum threshold, and for blocking the memory page at each occurrence of fault after the sum total number of occurrences of faults has exceeded the sum total threshold after switching before the number of occurrences in units of cache lines exceeds the threshold in units of cache lines. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011150469(A) 申请公布日期 2011.08.04
申请号 JP20100009992 申请日期 2010.01.20
申请人 NEC CORP 发明人 SEKIMOTO TAKAHITO
分类号 G06F12/16;G06F11/34 主分类号 G06F12/16
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