| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that the number of test data for confirming the validity of a logic circuit by simulation is increased according to the increase of confirmation contents, the increase of the scale of the logic circuit, and the increase of the number of combination states, and a time necessary for simulation is increased, and to solve the problem that the increase of the complexity of the logic circuit makes it difficult to create test data. SOLUTION: A logic verification system is configured to generate a test data/observation point correlation diagram by a test data/observation point correlation diagram generation function from the execution result obtained by simulating a logic circuit provided with an observation point and test data, and to visualize the correlation of the test data and the logic circuit operation part, and also to control the generation of the test data based on a feature extracted from the correlation diagram. COPYRIGHT: (C)2011,JPO&INPIT
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