| 摘要 |
<P>PROBLEM TO BE SOLVED: To efficiently transfer data between processors in a multi-processor having a shared cache memory. <P>SOLUTION: Each entry in a cache memory of a tag storage section 220 stores the number of times referenced 224 along with a tag address 221, a valid 222 and a dirty 223. The number of times referenced 224 is set when the data is written in and is decremented upon each read access. When the number of times referenced 224 is decremented from "1" to "0", the entry in question is invalidated without being written back. The cache memory functions as a shared FIFO memory when used for communication between the processors in a multi-processor system, and data that have been used are deleted automatically. <P>COPYRIGHT: (C)2011,JPO&INPIT |
