发明名称 Method of placing and routing for power optimization and timing closure
摘要 A method, algorithm, software, architecture and/or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one embodiment, a method of placing and routing can include: (i) routing signal paths in one or more upper metal layers for connecting circuit blocks; (ii) adjusting the circuit blocks based on electrical characteristics of the signal paths; and (iii) routing in one or more lower metal layers connections between the circuit blocks and the upper layers. The circuit blocks can include standard cells, blocks, or gates configured to implement a logic or timing function, other components, and/or integrated circuits, for example. Embodiments of the present invention can advantageously reduce power consumption and improve timing closure in an automated place-and-route flow.
申请公布号 US7992122(B1) 申请公布日期 2011.08.02
申请号 US20050093713 申请日期 2005.03.25
申请人 GG TECHNOLOGY, INC. 发明人 BURSTEIN MICHAEL;GINZBURG BORIS
分类号 G06F17/50 主分类号 G06F17/50
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