| 摘要 |
A modular Gray code counter of arbitrary bit length having identical Gray code counter cells in every bit position. Each cell comprises a Toggle Flop and logic which triggers the Toggle Flop and sets the state of the Gray code counter cell. The two outputs of a cell feed two inputs of the next more significant cell. A parity flip-flop provides odd parity, and as a third input to the cell together with the other two inputs determines the state of the cell.
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