System and method for testing a large memory area during processor design verification and validation

摘要

A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test case set (multiple test cases) along with an initial address translation buffer that includes real addresses that reference an initial memory block. A test case executor modifies the real addresses after each test case set re-execution in order for a processor to test each replicated memory block included in the main memory.