Method and apparatus for translating a verification process having recursion for implementation in a logic emulator

摘要

Method and apparatus for translating a verification process having recursion for implementation in a logic emulator are described. Examples of the invention relate to a method, apparatus, and computer readable medium for translating a verification process for implementation in a hardware emulator of a logic verification system. A recursive task called by the verification process is identified. A copy of the recursive task is incorporated into the verification process. Interface registers are instantiated for the recursive task. Control flow transfer points are defined in the verification process. Calls of the recursive task are converted in the verification process to constructs for accessing the interface registers and transferring control flow among the control flow transfer points. The verification process is reorganized to describe a finite state machine (FSM) configured for implementation in the hardware emulator.