发明名称 |
Stacked Integracted Circuit Verification |
摘要 |
Techniques for performing physical verification processes for stacked integrated circuit devices. An interface between a first two-dimensional integrated circuit device and a second two-dimensional integrated circuit device is identified. The design data for the identified layers in the first and second two-dimensional integrated circuit devices are then combined and physically verified as a single set of interface design data. The design data for the first two-dimensional integrated circuit device and the second two-dimensional integrated circuit device are then separately physically verified. Once the interface design data, the first two-dimensional integrated circuit device design data and the second two-dimensional integrated circuit device design data have been physically verified, the verified design can be recombined to form verified design data corresponding to a stacked integrated circuit device.
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申请公布号 |
US2011185323(A1) |
申请公布日期 |
2011.07.28 |
申请号 |
US20100861824 |
申请日期 |
2010.08.23 |
申请人 |
HOGAN WILLIAM MATTHEW;PETRANOVIC DUSAN;ASLYAN ARA |
发明人 |
HOGAN WILLIAM MATTHEW;PETRANOVIC DUSAN;ASLYAN ARA |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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