| 摘要 |
PROBLEM TO BE SOLVED: To reproduce trouble having occurred in hardware model simulation in logic verification with small man-hours, in verification work of an SoC (System on Chip) device. SOLUTION: A software model of the SoC device is operated according to a test program having made the trouble occur in the hardware model simulation, and memory access, an update wait of a memory, register access, and an update wait of a register occurring in a process of the operation are recorded in a log in order of the occurrence while each of them is converted into an RTL (Register Transfer Logic). The logic verification is executed with the log as a test task. COPYRIGHT: (C)2011,JPO&INPIT
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