发明名称 PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
摘要 Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
申请公布号 US2011183481(A1) 申请公布日期 2011.07.28
申请号 US201113080903 申请日期 2011.04.06
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 DYER THOMAS W.
分类号 H01L21/336 主分类号 H01L21/336
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