发明名称 Serial cancellation receiver design for a coded signal processing engine
摘要 An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.
申请公布号 US2011182330(A1) 申请公布日期 2011.07.28
申请号 US201113076332 申请日期 2011.03.30
申请人 RAMBUS INC. 发明人 OLSON ERIC S.;NARAYAN ANAND P.;THOMAS JOHN K.
分类号 G01S19/48;H04B1/10;G01S1/00;G01S5/02;G01S5/10;G01S5/14;H04J11/00 主分类号 G01S19/48
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