发明名称 PLL oscillator circuit
摘要 Disclosed is a PLL oscillator circuit capable of examining an unlock state while being equipped with an auto retry function enabling automatic relock. In the PLL oscillator circuit, a MPU receives a lock detection signal from the PLL-IC that receives an external reference signal and an output signal from a VCXO and outputs a control voltage to the VCXO, sets data for unlock alarm test at the PLL-IC, the data turning a lock state into an unlock state, when determining an unlock state with the lock detection signal from the PLL-IC, outputs an unlock alarm output signal to the outside, determines whether the unlock state continues for a first time period, and when the unlock state continues for the first time period, executes retry to set data for relock at the PLL-IC.
申请公布号 US2011181327(A1) 申请公布日期 2011.07.28
申请号 US20110929380 申请日期 2011.01.20
申请人 SHIOBARA TSUYOSHI 发明人 SHIOBARA TSUYOSHI
分类号 H03L7/08 主分类号 H03L7/08
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