发明名称 PROCESS FOR FABRICATING A HETEROSTRUCTURE WITH MINIMIZED STRESS
摘要 <p>PROCESS FOR FABRICATING A HETEROSTRUCTURE WITH MINIMIZED STRESSProcess for fabricating a heterostructure comprising a step (S5) of bonding a first wafer (110) to a second wafer (120), the first wafer (110) having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer (120), and at least one bond-strengthening annealing step (S7). The process is particularly characterized in that it comprises, after the bonding step (S5) and before the bond-strengthening annealing step (S7), at least one trimming step (S5) in which the first wafer (110) is at least partially trimmed.(Figures 4C & 4D)</p>
申请公布号 SG172528(A1) 申请公布日期 2011.07.28
申请号 SG20100077055 申请日期 2010.10.20
申请人 S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES 发明人 VAUFREDAZ, ALEXANDRE
分类号 (IPC1-7):H01L21/304;H01L21/762 主分类号 (IPC1-7):H01L21/304
代理机构 代理人
主权项
地址