| 摘要 |
A source driver includes a dividing circuit, a start signal capturing unit, a pulse width determining unit and a control circuit. The dividing circuit produces a divided clock by dividing a basic clock signal. The start signal capturing unit captures the start signal at timing of the edge of the divided clock. The pulse width determining unit determines a pulse width of the start signal that is captured. The control circuit changes the timing to start capturing the data according to the pulse width of the start signal. With this structure, the latter source driver is able to adjust capturing timing to effective data timing input thereto, even though final data does not end at the falling edge of the divided clock signal.
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