发明名称 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
摘要 In order to 3-dimensionally implement a semiconductor device, implant a conductive material in an opening having a narrow pitch, a very small diameter and a high aspect ratio, without forming a gap, thus forming a through electrode at low cost. Use a conductive adhesive layer to bond a conductive support substrate on the surface of a semiconductor substrate whereon an insulating layer and pad electrodes are formed. In this state, polish the rear surface of the semiconductor surface and after the surface has thinned openings are formed. Then, simultaneously apply the same electrical potential to the plurality of pad electrodes via the support substrate and the adhesive layer, and implant copper into the openings using a bottom-up growth plating method, thus forming through electrodes formed from a Cu plug and a Cu post. Due to this method, the aspect ratio of the openings is not extremely high, and thus copper can be implanted effectively and the number of manufacturing steps involved in reversing the front and rear sides of a semiconductor substrate can be reduced.
申请公布号 WO2011089677(A1) 申请公布日期 2011.07.28
申请号 WO2010JP07470 申请日期 2010.12.24
申请人 PANASONIC CORPORATION;UEDA, TETSUYA 发明人 UEDA, TETSUYA
分类号 H01L21/3205;H01L23/12;H01L23/52;H01L25/065;H01L25/07;H01L25/18 主分类号 H01L21/3205
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