| 摘要 |
PURPOSE: A receiving circuit, an information processing apparatus and a buffer control method are provided to cut a deskew buffer existing in the receiving circuit, thereby enabling smaller latency of the receiving circuit. CONSTITUTION: A receiving circuit(301) comprises a lane block and a multi lane control circuit(303). A gear box(312) writes DATA_4BIT(321) of four bit-widths to a RX_CLOCK_DIVIDE_4 clock. An elastic buffer(314) deciphers DATA_10BIT(324) data and outputs to a pattern detecting circuit(315) and 8B10B converting circuit(316). The pattern detecting circuit outputs a signal controlling a read address to the elastic buffer. The 8B10B converting circuit coverts 10b-code data into 8b-code DATA_8BIT(325) data. |
