| 发明名称 |
Shallow trench avoidance in integrated circuits |
| 摘要 |
<p>Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.</p> |
| 申请公布号 |
GB2447196(B) |
申请公布日期 |
2011.07.27 |
| 申请号 |
GB20080012517 |
申请日期 |
2007.03.21 |
| 申请人 |
INTEL CORPORATION |
发明人 |
JEFFREY DAVIS;RAJASHRI DODDAMANI;BYUNGHA JOO;DUC NGUYEN;DARSHANA SURTI;EVA YIM |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
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代理人 |
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