| 摘要 |
PURPOSE: A clock jitter suppression method and a computer-readable storage medium are provided to suppress the clock jitter of a semiconductor IC through a short time and low costs. CONSTITUTION: In a clock jitter suppression method and a computer-readable storage medium, an arbitrary logical value is set in a memory device(S1). The threshold voltage of the memory device is varied. The value maintained in the memory device is determined(S4) An analysis process is performed(S6) The analysis process specifies the interference to power voltage and ground voltage of a clock buffer due to noise. The arrangement of a component or a limit condition of a wring is made(S7). The rearrangement and rewiring of the component is performed(S8). The rearrangement changes the limit condition.
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