发明名称 Caching in multicore and multiprocessor architectures
摘要 A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
申请公布号 US7987321(B1) 申请公布日期 2011.07.26
申请号 US20100966686 申请日期 2010.12.13
申请人 TILERA CORPORATION 发明人 AGARWAL ANANT;BRATT IAN R.;MATTINA MATTHEW
分类号 G06F12/00 主分类号 G06F12/00
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