| 摘要 |
A circuit, such as, but not limited to, a digital phase-locked loop (PLL) or a transport timing loop, uses a fractional-N modulator and a fractional-N clock synthesizer to generate a clock signal, such as a transmit clock signal, from a reference clock signal. One embodiment uses a recovered clock signal derived from serial received data as a positive input to a feedback loop, and uses the transmit clock signal as a negative input to the feedback loop. After digital phase detection and digital filtering, a filtered error signal s is generated and used to control a modified fraction for control of the fractional-N synthesizer. Disclosed techniques advantageously exhibit jitter attenuation and have relatively little jitter accumulation, which are useful characteristics in telecommunication and data communication network clocking applications. Embodiments can be applied to loop timing, clock regeneration, and transport timing applications, and can be used when clock holdover is desirable.
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