发明名称 Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices
摘要 A PLD includes at least one IP block or circuit, and at least one I/O block or circuit. The performance of the at least one IP block is adjusted in order to meet at least one performance characteristic by changing a supply level of the at least one IP block, by adjusting at least one body bias level of the IP block, or both. The performance of the at least one I/O block is adjusted by changing a supply level of the at least one I/O block, by adjusting at least one body bias level of the I/O block, or both.
申请公布号 US7986160(B2) 申请公布日期 2011.07.26
申请号 US20060420737 申请日期 2006.05.27
申请人 ALTERA CORPORATION 发明人 HOANG TIM TRI;SHUMARAYEV SERGEY
分类号 H03K17/16;H03K19/173 主分类号 H03K17/16
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