发明名称 |
Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension |
摘要 |
A method for performing multiplication on a field programmable gate array includes generating a product by multiplying a first plurality of bits from a first number and a first plurality of bits from a second number. A stored value designated as a product of a second plurality of bits from the first number and a second plurality of bits from the second number is retrieved. The product is scaled with respect to a position of the first plurality of bits from the first number and a position of the first plurality of bits from the second number. The stored value is scaled with respect to a position of the second plurality of bits from the second number and a position of the second plurality of bits from the second number. The scaled product and the scaled stored value are summed.
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申请公布号 |
US7987222(B1) |
申请公布日期 |
2011.07.26 |
申请号 |
US20040829559 |
申请日期 |
2004.04.22 |
申请人 |
ALTERA CORPORATION |
发明人 |
HAZANCHUK ASHER;ESPOSITO BENJAMIN |
分类号 |
G06F7/38 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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