发明名称 Semiconductor memory device and redundancy method therefor
摘要 A memory cell array is formed by arranging memory cells at intersections of plural first wirings and plural second wirings, and a rectifying element and a variable resistive element are connected in series in the memory cell. The variable resistive element has at least a first resistance value and a second resistance value that is higher than the first resistance value. The control circuit selectively drives the first wirings and the second wirings. The control circuit can perform a short-circuit failure countermeasure program operation. In the short-circuit failure countermeasure program operation, the variable resistive element of the memory cell whose rectifying element is in a short-circuit failure state is programmed from the first resistance value to the second resistance value.
申请公布号 US7986575(B2) 申请公布日期 2011.07.26
申请号 US20090414083 申请日期 2009.03.30
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 INABA TSUNEO
分类号 G11C29/00;G11C7/00 主分类号 G11C29/00
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