摘要 |
Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material. |
申请人 |
INTEL CORPORATION;PILLARISETTY, RAVI;KAVALIEROS, JACK, T.;CHU-KUNG, BENJAMIN;RACHMADY, WILLY;HUDAIT, MANTU, K.;MUKHERJEE, NILOY;RADOSAVLJEVIC, MARKO;CHAU, ROBERT, S. |
发明人 |
PILLARISETTY, RAVI;KAVALIEROS, JACK, T.;CHU-KUNG, BENJAMIN;RACHMADY, WILLY;HUDAIT, MANTU, K.;MUKHERJEE, NILOY;RADOSAVLJEVIC, MARKO;CHAU, ROBERT, S. |