发明名称 CLOCK AND DATA RECOVERY FOR BURST-MODE SERIAL SIGNALS
摘要 A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.
申请公布号 WO2011088369(A2) 申请公布日期 2011.07.21
申请号 WO2011US21367 申请日期 2011.01.14
申请人 VITESSE SEMICONDUCTOR CORPORATION;KYLES, IAN;PAHOMSKY, EUGENE 发明人 KYLES, IAN;PAHOMSKY, EUGENE
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