发明名称 |
CONTROLLING TIME STAMP COUNTER (TSC) OFFSETS FOR MULITPLE CORES AND THREADS |
摘要 |
In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed. |
申请公布号 |
WO2011087558(A2) |
申请公布日期 |
2011.07.21 |
申请号 |
WO2010US56165 |
申请日期 |
2010.11.10 |
申请人 |
INTEL CORPORATION;DIXON, MARTIN;SHRALL, JEREMY J.;PARTHASARATHY, RAJESH S. |
发明人 |
DIXON, MARTIN;SHRALL, JEREMY J.;PARTHASARATHY, RAJESH S. |
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