STRAINED TRANSISTOR INTEGRATION FOR CMOS

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor device that is improved in electron mobility of an n-type MOS device (NMOS) and improved in hole mobility of a p-type MOS device (PMOS).

SOLUTION: The CMOS device has (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

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