Methods and systems for providing variable clock rates and data rates for a SERDES

摘要

A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock frequency is shown. According to this method and apparatus, a PMA rate signal may control the frequency of the output clock while a datastrobe signal may be used to control the frequency of the data signal. Accordingly, the apparatus and methods may be used to produce an output data signal and a clock signal having frequencies that may be lower than the frequency of the input clock signal.