发明名称 |
System and method for random defect yield simulation of chip with built-in redundancy |
摘要 |
In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.
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申请公布号 |
US7984399(B1) |
申请公布日期 |
2011.07.19 |
申请号 |
US20070965681 |
申请日期 |
2007.12.27 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
RUEHL ROLAND;KOSHY MATHEW;FALES JONATHAN;GUMASTE UDAYAN |
分类号 |
G06F17/50;G06F9/455 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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