| 摘要 |
In a conventional manufacturing process where the number of manufacturing processes is reduced to form a semiconductor layer of a channel etch-type insulating gate-type transistor and source-drain wires in one photographic etching processing using half-tone exposure technology, the manufacturing margin is narrow, lowering the yield if the distance between the source and the drain wire shortens. A 4-mask process proposal needless of half-tone exposure technology is constructed by streamlining the formation of scan lines and pseudo-pixel electrodes at the same time, both comprising a laminate of a transparent conductive layer and a metal layer, and the formation of the transparent conductive pixel electrodes through removing the metal layers on the pseudo-pixel electrodes at the time of the formation of the opening in the passivation insulating layer, as well as by reducing the formation process of the opening through removing a gate insulating layer also at the formation of semiconductor layers for channel-etch type insulating gate transistors. |
