发明名称 Method for reducing the reactive power requirement of a fundamental frequency clocked power supply side converter under no load and with low motor loading
摘要 The invention relates to a method for reducing the idle current requirement of a base frequency clocked supply side converter (1) on idle and with low motor loads, provided with controllable semiconductors (T1,T2,T3,T4, T5,T6), wherein the base frequency clocking of the semiconductor switches (T1,T2,T3,T4,T5,T6) occurs depending on the desired direction of flow of power. A converter (1) for carrying out said method is also disclosed.
申请公布号 US7983060(B2) 申请公布日期 2011.07.19
申请号 US20070295127 申请日期 2007.02.21
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 BENESCH NORBERT
分类号 H02M0003/000045 主分类号 H02M0003/000045
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