发明名称 Dynamic circuit with slow mux input
摘要 A logic circuit includes a control circuit including a first logic gate to receive a selection signal and a first input signal and to output a pulse control signal and a second logic gate to receive the pulse control signal, a clock signal, and a delayed clock signal and to output a pulse signal, and a multiplexing logic circuit to receive the selection signal and the pulse signal from the control circuit, to receive at least one second, static input signal, and to output a signal corresponding to one of the first input signal and the second, static input signal based on the state of the selection signal.
申请公布号 US7982503(B2) 申请公布日期 2011.07.19
申请号 US20100814635 申请日期 2010.06.14
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM MIN-SU
分类号 H03K19/096 主分类号 H03K19/096
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