发明名称 JITTER REMOVING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem with a conventional circuit, wherein jitter is generated in a clock which is generated by a reference clock generation circuit. <P>SOLUTION: A jitter removing circuit removes the jitter of a reference clock 51, and includes: a latch circuit 12 which detects edges of the reference clock 51 in synchronism with a sampling clock 52; a counter 13 which counts edge intervals of the reference clock 51; and a phase adjustment circuit 14 which adjusts a phase of the reference clock 51 on the basis of the number of counts of the respective edge intervals. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011139285(A) 申请公布日期 2011.07.14
申请号 JP20090297824 申请日期 2009.12.28
申请人 RENESAS ELECTRONICS CORP 发明人 YOSHINO TAKASHI
分类号 H03L7/00;H03K5/04 主分类号 H03L7/00
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