发明名称 ERROR CONTROLLER, PROCESSOR CORE, ARITHMETIC PROCESSOR, INFORMATION PROCESSOR, AND PSEUDO ERROR CONTROL METHOD
摘要 <P>PROBLEM TO BE SOLVED: To obtain an error controller in consideration of the propagation delay of a signal on the generation of a pseudo error, and also to provide a processor core, and a pseudo error control method. <P>SOLUTION: Pseudo error generating devices 30_1 to 30_n for generating the pseudo error are arranged in the neighborhood of error generation target circuits 40_1 to 40_n. A pseudo error controller 20 selects one of the pseudo error generating devices 30_1 to 30_n and sets an error content in a local error mode register 31. The pseudo error generating devices 30_1 to 30_n monitor the generation of an event corresponding to the error content so as to notify the pseudo error controller 20 of the generation. The pseudo error controller 20 instructs the generation of the error to the pseudo error generating devices 30_1 to 30_n, based on the times of generation of the event. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011138211(A) 申请公布日期 2011.07.14
申请号 JP20090296260 申请日期 2009.12.25
申请人 FUJITSU LTD 发明人 YAMAZAKI IWAO
分类号 G06F11/22 主分类号 G06F11/22
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