| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve charging performance of a bit line even if parasitic capacity between the adjacent bit lines increases; and to achieve high speed charging. <P>SOLUTION: A nonvolatile semiconductor memory includes a memory cell transistor, a word line, a row decoder, the bit line, a sense amplifier determining data of the memory cell transistor through the bit line, a first bit line clamp transistor connected between the bit line and the sense amplifier in series, a second bit line clamp transistor which is connected in parallel to the first bit line clamp transistor and has higher current driving capacity than the first bit line clamp transistor, and a bit line control circuit turning on the first and second bit line clamp transistors by common gate voltage in a prescribed period from charging start of the bit line and turning off only the second bit line clamp transistor after the prescribed period elapses. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
