发明名称 VERIFICATION SUPPORT PROGRAM AND VERIFICATION SUPPORT DEVICE
摘要 PROBLEM TO BE SOLVED: To prevent false determination by accurately verifying any false operation caused in a meta stable state. SOLUTION: A circuit model 1 and a circuit model 2 are configured to have the same function. In the first model 1, a reception FF in a reception clock domain is a normal FF model. In the second model 2, the reception FF in the reception clock domain is a CDC model. A verification support device detects a change in variables (rstate) showing the state of the reception clock domain in the circuit model 1, and detects a change in the variables (rstate) showing the state of the reception clock domain in the circuit model 2. The verification support device successively holds the states at the time of detecting the state change, and determines whether a series of held states are different from each other. When determining any difference, the verification support device outputs information indicating that a false occurs. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011138183(A) 申请公布日期 2011.07.14
申请号 JP20090295906 申请日期 2009.12.25
申请人 FUJITSU LTD 发明人 IWASHITA HIROAKI
分类号 G06F17/50 主分类号 G06F17/50
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