发明名称
摘要 <p>In a time measuring circuit, a pulse delay circuit is provided with a plurality of delay units. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on a level of a first drive voltage being input to each of the plurality of delay units. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate, as time measurement data, digital data based on the obtained number. A first setting unit is configured to variably set the level of the first drive voltage being input to each of the plurality of delay units.</p>
申请公布号 JP4725418(B2) 申请公布日期 2011.07.13
申请号 JP20060152331 申请日期 2006.05.31
申请人 发明人
分类号 G04F10/04;H03K5/14;H03K5/26;H03M1/50 主分类号 G04F10/04
代理机构 代理人
主权项
地址