发明名称 High speed interface for multi-level memory
摘要 A solid state memory system includes a first memory chip that includes a plurality of storage elements, and a controller. Each of the plurality of storage elements have a measurable parameter that varies between a lower limit and an upper limit. The controller receives write data, converts the write data to N target values, and transmits the N target values to the first memory chip. The first memory chip adjusts corresponding measurable parameters of N storage elements of the plurality of storage elements to the N target values, where N is an integer greater than zero.
申请公布号 US7978541(B2) 申请公布日期 2011.07.12
申请号 US20070966009 申请日期 2007.12.28
申请人 MARVELL WORLD TRADE LTD. 发明人 SUTARDJA PANTAS
分类号 G11C7/00;G11C7/22 主分类号 G11C7/00
代理机构 代理人
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