| 摘要 |
A data driving circuit including n channels, where n is an integer, the data driving circuit including a shift register unit receiving data during a first input period and a second input period, the shift register unit shifting and outputting the received data, a first latch unit receiving the data input during the first input period from the shift register unit, and simultaneously or substantially simultaneously outputting the data corresponding to the first input period, and a second latch unit receiving the data input during the second input period from the shift register unit, and simultaneously or substantially simultaneously outputting the data corresponding to the second input period.
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