发明名称 Apparatus for manufacturing a multilayer chip capacitor
摘要 The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.
申请公布号 US7975371(B2) 申请公布日期 2011.07.12
申请号 US20060914498 申请日期 2006.06.21
申请人 SEHYANG INDUSTRIAL CO., LTD. 发明人 HA JAE-HO
分类号 H05K3/30 主分类号 H05K3/30
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