| 摘要 |
A periodic pulse sequence former is proposed, pulse width is determined by control signal width. The former comprises two binary counters, first of which has clock input, summation/countdown input, synchronous parallel load enable input, loading data input, counting enable input, asynchronous zero set input, overflow input, invertor 3, two OR elements, a circuit comprising in series connected resistor and capacitor, start/stop apparatus comprises synchronous flip-flop having asynchronous zero set input, first and second two-input AND element. Second accumulating counter is incorporated, it comprises clock input, counting enable input, and zero set input. |
