| 摘要 |
A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary variables, including a first network of cells implementing logic functions on the first component of the pairs and a second network of dual cells operating in complementary logic on the second component of the pair. A calculation step includes a precharge phase, in which the variables are put into a known state at the output of the cells, and an evaluation phase in which a calculation is made by the cells. A phase of synchronizing the variables is inserted before the evaluation phase or the precharge phase in each cell capable of receiving several signals conveying input variables, the synchronization being carried out on the most delayed signal.
|
