发明名称 PEAK HOLDING CIRCUIT, AND OUTPUT VOLTAGE CONTROL CIRCUIT INCLUDING THE PEAK HOLDING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a technique for making compact an output voltage control circuit which controls the output voltage of a power supply circuit, supplying an operating voltage to a speaker amplifier, in accordance with the operation state of the speaker amplifier. SOLUTION: The peak holding circuit, included in an output voltage control circuit which performs operation control over the power supply which is supplied with a plus voltage BVDD and a ground voltage VSS, and supplies the potential difference between the plus voltage VPP and minus voltage VMM to each speaker amplifier as the operating voltage, includes first and second P-channel FETs which are supplied at drains thereof with an output voltage VMM and applied at gates thereof with output voltages of respective speaker amplifiers, and a third P-channel FET which is supplied at the drain and gate thereof with the ground voltage VSS, as three P-channel FETs (field-effect transistors) having sources thereof connected in common, and outputs a voltage generated at the common connection point of the sources thereof. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011135413(A) 申请公布日期 2011.07.07
申请号 JP20090294003 申请日期 2009.12.25
申请人 YAMAHA CORP 发明人 TSUJI NOBUAKI
分类号 H03F1/02;H03F3/181;H03F3/20;H03F3/68 主分类号 H03F1/02
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