| 摘要 |
<p>PURPOSE: A semiconductor device is provided to prevent an alignment error of a PEP process by increasing the recognition rate of an alignment key by preventing erosion or dishing in a planarization process. CONSTITUTION: An interlayer insulation layer(310) is laminated on a substrate(300). A via hole(320) is formed in the interlayer insulation layer. A contact plug is formed on a circuit pattern area. An alignment key(330) is formed on the alignment key forming area. A dummy oxide layer(340) is formed between the alignment keys to control the pattern density of the alignment key in a damascene process.</p> |
