A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
申请公布号
WO2011081811(A2)
申请公布日期
2011.07.07
申请号
WO2010US59461
申请日期
2010.12.08
申请人
INTEL CORPORATION;TONG, XIANGHONG;CHEN, ZHANPING;MA, ZHIYONG;JOHNSON, KEVIN D.;HE, JUN;ZHANG, KEVIN X.
发明人
TONG, XIANGHONG;CHEN, ZHANPING;MA, ZHIYONG;JOHNSON, KEVIN D.;HE, JUN;ZHANG, KEVIN X.